`timescale 1ns / 1ps

module dlatch_sim;
    reg D,RST,EN;
    wire Q,QN;
    dlatch d0(Q,QN,D,RST,EN);
    initial begin
        D=0;RST=0;EN=0;
        fork
            #5 D=~D;
            #10 RST=~RST;
            #20 EN=~EN;
        join
        end
endmodule
